Multilevel metallization process for electronic components
US5380546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1993 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Jun 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4644
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A maskless process for forming a protected metal feature in a planar insulating layer of a substrate is disclosed. A first barrier material is disposed in a recess in an insulating layer, a conductive metal is disposed on the first barrier material such that the entire metal feature is positioned within the recess below the top of the recess, a second barrier material is disposed on the metal feature such that the second barrier material occupies the entire portion of the recess above the metal feature and extends above the top surface of the insulating layer, and the second barrier material is then polished until the top of the second barrier material is in and aligned with the top of the insulating layer. As a result, the metal feature is surrounded and protected by the first and second barrier materials, and the substrate is planarized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.