Dram capacitor structure

US5380673A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Ming-Tzong Yang · Baoshan, TW
• Chen-Chiu Hsue · Baoshan, TW
• Anchor Chen · Pingtung City, TW

Key dates

• Filing date: May 6, 1994
• Grant date: Jan 10, 1995
• Expiry date: May 6, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A new structure and method for fabricating a stacked capacitor with increased capacitance and which is more manufacturable was accomplished. The stacked capacitor is part of a dynamic random access memory (DRAM) cell for storing charge on the capacitor and together with a field effect transistor (MOSFET) make up the individual DRAM storage cells on a DRAM chip. Fabricating this improved stacked capacitor involves using an additional electrically conducting layer in the polysilicon layer of the bottom electrode. For example, this layer can be composed from materials in the metal nitride group having high conductivity. One preferred choice being titanium nitride (TiN). The bottom electrode is formed by depositing and patterning a thin layer of polysilicon and a thin layer of the electrically conducting layer and then depositing an upper layer of polysilicon from which vertical sidewalls are formed. The conducting layer provides an etch end point for accurately etching to the correct depth. This provided for a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and formin…