Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction
US5381531A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 1991 |
| Grant date | Jan 10, 1995 |
| Priority date | — |
| Expiry date | Jul 9, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.