High voltage CMOS device to integrate low voltage controlling device
US5382820A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1993 |
| Grant date | Jan 17, 1995 |
| Priority date | — |
| Expiry date | Dec 8, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/858
Abstract
A method of fabrication of an semiconductor device comprises applying an impurity of a predetermined polarity to a silicon substrate; forming a well by applying an impurity of an opposite polarity to a region in the silicon substrate; forming a first masking layer on the surface of the substrate; providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first regions selected in the substrate and the well forming a second masking layer on the surface of the substrate; implanting dopant ions of a second polarity through a second mask in other regions selected in the well and the substrate; removal of the second masking layer; formation of field oxide structures over the first and second regions; forming gate oxide layers above the exposed portions of the first and second central regions; and formation of conductive gate structures over the gate oxide layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.