Per-wafer method for globally stressing gate oxide during device fabrication
US5391502A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Aug 27, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate oxide on a semiconductor wafer is effectively stressed on a per-wafer basis during fabrication. Because it was effectively stressed, gross testing the gate oxide after device fabrication provides a good indication whether a completed MOS device will be subject to infant mortality. After the gate oxide is formed, a source of overvoltage may be coupled between the raw oxide and the underside of the wafer, to accelerate stress due to defects in the oxide. Alternatively, the oxide may be stressed after deposition of the gate material by coupling a source of overvoltage directly to the gate material and to a probe on the underside of the wafer. The oxide may also be stressed after patterning and definition of the gate material by coupling a source of over-voltage to all of the gates simultaneously, preferably using a mercury probe, plasma or a conductive conforming membrane, and to a probe on the underside of the wafer. The overvoltage is sufficiently large to stress defect-containing oxide, but not to breakdown good oxide. After stress, prior art procedures to complete fabrication, post-fabrication burn-in and testing may be carried out. Because the present invention effectively s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.