Method of producing VDMOS transistors
US5395777A · kind A · utility
9Cited by
7References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 6, 1994 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Apr 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
A method of producing reduced-size VDMOS transistors having reduced leakage and a reduced propensity to latch-up. These advantages are attained by reducing the vertical projective area of the source electrodes of the VDMOS transistors. This is done by forming first trenches which are sufficiently deep to reach an epitaxial layer on a substrate of the VDMOS transistors before second trenches are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.