Chemical-mechanical polishing processes of planarizing insulating layers
US5395801A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1993 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Sep 29, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor processing method of providing and planarizing an insulating layer on a semiconductor wafer includes the following sequential steps: a) providing a conformal layer of insulating material to a first thickness over a semiconductor wafer having non-planar topography; b) providing a CMP polishing protective layer over the conformal layer to a second thickness, the protective layer being of different composition than the conformal layer; and c) chemical-mechanical polishing the protective layer and conformal layer in a single CMP step using a single CMP slurry and under conditions which in combination with the slurry remove the conformal layer material at a faster rate than the protective layer material, the protective layer upon outward exposure of conformal layer material in high topographical areas restricting material removal from low topographical areas during such chemical-mechanical polishing. Alternately, the protective layer and conformal layer are CMPed in at least two steps using first and second respective CMP slurries. The first CMP step and slurry remove outermost portions of the protective layer in a manner which is substantially selective to the underlyin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.