Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors
US5397722A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1994 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Jul 11, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/02
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming field effect transistors having self-aligned source/drain contact includes: forming an gate overlying a portion of a semiconductor; forming a first sidewall spacer on the gate; forming a source/drain region in the semiconductor; depositing a conductive layer over the semiconductor so that a step is formed in the conductive layer in a region overlying the gate and the first sidewall spacer; forming a second sidewall spacer on the step; forming a protective layer over a portion of the conducting layer not covered by the second sidewall spacer; removing the second sidewall spacer to expose a portion of the conductive layer but leave covered a portion of the conductive layer underlying the protective layer; and removing the exposed portion of the conductive layer to leave a portion of the conductive layer in contact with the source/drain region and electrically isolated from the gate. The portion of the conductive layer left is the self-aligned contact. Typically, the conductive layer is polysilicon but may alternatively be polysilicide or silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.