Process for forming a semiconductor device having a capacitor
US5409855A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1992 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Oct 13, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A method for making a semiconductor memory cell having a storage capacitor disposed between metallization layers. Field and active regions and transistor circuit elements are formed on a substrate, on which is formed an insulating layer. A bit line is formed through a contact formed in the insulating layer. Another insulating layer is formed and a contact is formed to a word line and transistor and a primary metallization layer is formed of a refractory metal or metal compound. An oxide and an insulating layer are formed, and a buried contact to a source/drain region of a memory access transistor is formed to have an oxide side wall, and the storage electrode, dielectric and plate electrode are formed thereon. A secondary metallization layer may also be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.