Blanket N-LDD implantation for sub-micron MOS device manufacturing

US5413945A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Sun-Chieh Chien · Hsinchu, TW
• Tzong-Shien Wu · Hsinchu, TW

Key dates

• Filing date: Aug 12, 1994
• Grant date: May 9, 1995
• Expiry date: Aug 12, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over the P-well and N-well regions is provided. The P-well region is implanted, in a substantially vertical direction, with a first conductivity-imparting dopant. Gate structures are formed over the P-well and N-well regions. A second conductivity-imparting dopant is implanted, at a large angle to the plane of the silicon substrate, that is of opposite conductivity to the first conductivity-imparting dopant, into the P-well and N-well regions, masked by the gate structures. The N-well region is implanted, in a substantially vertical direction, with a third conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. Sidewall spacers are formed on the gate structures. The P-well region is implanted, in a substantially vertical direction, with a fourth conductivity-imparting dopant, of the same conductivity as the second conductivity-imparting dopant. The N…