Method of forming a DRAM stacked capacitor cell
US5413950A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1994 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Apr 22, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/711
Abstract
A new stacked capacitor structure having increased capacitance and a method of fabrication was accomplished. The capacitor stores data in the form of stored charge and together with a field effect transistor (MOSFET) make up the individual Dynamic Random Access Memory (DRAM) storage cells on a DRAM chip. The improved capacitor is fabricated using an electrically conducting layer in the bottom electrode of the capacitor, which is substantially different in composition from silicon. The conducting layer preferably being a refractory metal or a refactory metal silicides, such as, tungsten (W) or tungsten silicide (WSi). The bottom electrode is formed from a multilayer composed of a thin polysilicon layer, the conducting layer and an upper thicker polysilicon layer. Vertical capacitor sidewalls are formed from the upper polysilicon layer by photoresist masking and then etching to the conducting layer. The conducting layer provides an etch end point for accurately etching to the correct depth without over etching. This provides a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom el…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.