Vertical transistor having an underlying gate electrode contact
US5414288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1994 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Feb 16, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.