Dynamic memory device having a vertical transistor
US5414289A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1993 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Nov 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.