Semiconductor memory device with additional conductive line to prevent line breakage
US5416347A · kind A · utility
17Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1992 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | Oct 13, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.