Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication
US5420796A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1993 |
| Grant date | May 30, 1995 |
| Priority date | — |
| Expiry date | Dec 23, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/854
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the semiconductor devices. A dielectric layer is deposited over the metal layer and substrate. The dielectric layer is etched back to prepare for the deposition of additional metal and dielectric layers. The etched surface is scanned by an atomic force microscope (AFM) to gather data representing the wafer surface roughness. The data is evaluated by a computer to generate at least one surface roughness signal. Depending on the value of the surface roughness signal, the IC fabrication process continues with the next step, a remedial action is taken, the IC fabrication process is adjusted for subsequent wafers, or the wafer is discarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.