Process for fabricating high-voltage semiconductor power device
US5422286A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 1994 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | Oct 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a high-voltage semiconductor power device on a substrate of a first conductivity type is described. A lightly-doped epitaxial layer of the first conductivity type having a first thickness and a doped layer of a second conductivity type having a second thickness are then formed on the substrate. First grooves are formed by etching through the doped layer into the lightly-doped epitaxial layer. A pad oxide layer is formed on the exposed surfaces of the lightly-doped epitaxial layer and the doped layer. Silicon nitride spacers are formed on sidewalls of the first grooves. The thickness of portions of the pad oxide layer not covered by the silicon nitride spacers is increased by thermal oxidation. The silicon nitride spacers and portions of the pad oxide layer underlying the silicon nitride spacers are then removed. Second grooves are formed by etching through the bottoms of the first grooves and into the lightly-doped epitaxial layer using the remaining portions of the pad oxide as a mask. The remaining pad oxide is removed. Finally, a passivation layer and metal layers are formed completing the high-voltage semiconductor power device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.