Method for forming electrical isolation in an integrated circuit
US5422300A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1994 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | Aug 17, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Defect-free field oxide isolation is achieved using a laminated layer (14) of thermal silicon dioxide and chemically vapor deposited silicon dioxide underneath a silicon nitride field oxidation mask (18). The laminated layer (14) of silicon dioxide is formed on a silicon substrate (12) and a layer of silicon nitride is then deposited over it. The silicon nitride is subsequently patterned to form a field oxidation mask (18) which defines isolation regions (22) within the silicon substrate (12). Field oxide (34) is grown in the isolation regions (22) of the silicon substrate (12) and the field oxidation mask (18) is subsequently removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.