Prashant U. Kenkare
53Patents
12h-index
44Co-inventors
84Inventor score
Filing activity: Dec 3, 1992 → Sep 26, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7573762B2 | One time programmable element system in an integrated circuit | Physics | 71 | Active |
| US8004907B2 | SRAM with read and write assist | Physics | 46 | Active |
| US7369452B2 | Programmable cell | Physics | 41 | Active |
| US7843218B1 | Data latch with structural hold | Physics | 39 | Active |
| US7292495B1 | Integrated circuit having a memory with low voltage read/write operation | Physics | 25 | Active |
| US8120975B2 | Memory having negative voltage write assist circuit and method therefor | Physics | 25 | Active |
| US7864617B2 | Memory with reduced power supply voltage for a write operation | Physics | 23 | Active |
| US5236862A | Method of forming oxide isolation | Emerging Cross-Sectional Technologies | 19 | Expired |
| US5369052A | Method of forming dual field oxide isolation | Emerging Cross-Sectional Technologies | 17 | Expired |
| US8315117B2 | Integrated circuit memory having assisted access and method therefor | Physics | 17 | Active |
| US7542369B2 | Integrated circuit having a memory with low voltage read/write operation | Physics | 13 | Active |
| US8634263B2 | Integrated circuit having memory repair information storage and method therefor | Physics | 13 | Active |
| US7193924B2 | Dual-port static random access memory having improved cell stability and write margin | Physics | 12 | Expired |
| US5422300A | Method for forming electrical isolation in an integrated circuit | Electricity | 12 | Expired |
| US8059482B2 | Memory using multiple supply voltages | Physics | 12 | Active |
| US7671629B2 | Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains | Electricity | 11 | Active |
| US9330751B2 | SRAM wordline driver supply block with multiple modes | Physics | 11 | Active |
| US8975949B2 | Integrated clock gater (ICG) using clock cascode complimentary switch logic | Electricity | 10 | Active |
| US7492627B2 | Memory with increased write margin bitcells | Physics | 9 | Active |
| US8156357B2 | Voltage-based memory size scaling in a data processing system | Emerging Cross-Sectional Technologies | 9 | Active |
| US7548102B2 | Data latch with minimal setup time and launch delay | Electricity | 7 | Active |
| US8484523B2 | Sequential digital circuitry with test scan | Physics | 7 | Active |
| US7365587B2 | Contention-free keeper circuit and a method for contention elimination | Electricity | 5 | Active |
| US7489540B2 | Bitcell with variable-conductance transfer gate and method thereof | Physics | 5 | Active |
| US7623404B2 | Memory device having concurrent write and read cycles and method thereof | Physics | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.