Integrated circuit test arrangement and method for maximizing the use of tester comparator circuitry to economically test wide data I/O memory devices
US5422892A · kind A · utility
29Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1994 |
| Grant date | Jun 6, 1995 |
| Priority date | — |
| Expiry date | Aug 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.