Method for manufacturing a VDMOS transistor
US5424231A · kind A · utility
126Cited by
8References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1994 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Aug 9, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.