Semiconductor device including arrangement for reducing junction degradation
US5426326A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1993 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Aug 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/60
Abstract
An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided: EQU 4.3.times.10.sup.12 (/cm.sup.2).gtoreq.An.multidot.Xn.sup.2 =Ap.multidot.Xp.sup.2 Preferably, the p-n junction layer is formed under a contact hole of a source or drain region if the device in question is a MOSFET. As a result of using this arrangement…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.