Apparatus and method for improving the timing performance of a circuit
US5426591A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1994 |
| Grant date | Jun 20, 1995 |
| Priority date | — |
| Expiry date | Jan 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer aided design system and method for automatically modifying a specified Hardware Description Language (HDL) characterization of a circuit to reduce signal delays on critical paths of the circuit is described. The specified circuit is analyzed with a logic synthesizer including a novel cell-based timing verifier that determines if a circuit meets specified timing requirements. Timing requirements are tested by computing a slack value for each node of the circuit at the component (macrocell) level, where the slack value represents the difference between the required arrival time of a signal at each circuit node and the computed worst case signal arrival time for the node. The output node having the most negative slack value is identified as a critical node. The HDL description of the circuit corresponding to the critical node is modified with a synthesis directive to substitute the original datapath cell with a better cell in order to improve the circuit's timing performance. The revised HDL description of the circuit is then re-synthesized. Improvements to the circuit may be repeated in this fashion until the circuit meets all timing constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.