Method of forming a stacked capacitor using sidewall spacers and local oxidation
US5429980A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1994 |
| Grant date | Jul 4, 1995 |
| Priority date | — |
| Expiry date | Oct 5, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
Abstract
A method for fabricating a capacitors on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a field effect transistor (FET), having one capacitor aligned over and contacting the source/drain of the FET in the device region. The capacitor is increased in capacitance by forming a double recess in the bottom electrodes of the storage capacitors. The method of forming the double recess utilizes a sidewall spacer and local oxidation technique. After forming the bottom electrode having the double recess an insulating layer having a high dielectric constant is deposited as the inter-electrode insulator and a stop electrode is formed, completing the storage capacitor and the dynamic random access memory (DRAM) storage cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.