Method for fabricating self-aligned polysilicon contacts on FET source/drain areas
US5432105A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1994 |
| Grant date | Jul 11, 1995 |
| Priority date | — |
| Expiry date | Sep 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Improved N-channel and P-channel field effect transistor device structure having self-aligned polysilicon pads contacts and a process for making such devices has been achieved. The doped polysilicon pad contact are formed over the source/drain areas of the field effect transistors and are used to form shallow self-aligned diffused contact to the source/drain areas. These polysilicon pads provide a low resistance ohmic contacts that are free from implant damage that would otherwise cause increased junction leakage current and are free of metal spiking at the source/drain area perimeter that would cause metal contact to substrate shorts. The increased area of the polysilicon pads over the source/drain area allows for relaxed design ground rule for the contact openings, making for a more manufacturable process for Ultra Large Scale Integration applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.