Grounding method to eliminate the antenna effect in VLSI process
US5434108A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1993 |
| Grant date | Jul 18, 1995 |
| Priority date | — |
| Expiry date | Sep 22, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of subjecting an integrated circuit, having electrically grounded elements and large first metal regions on its surface which are connected to device structures, to a plasma process, is described. Large first metal regions are connected to the electrically grounded elements. The integrated circuit is placed in a chamber for accomplishing the plasma process. The integrated circuit is subjected to the plasma process such that the connecting of the large first metal regions to the electrically grounded elements prevents damage to the device structures. The integrated circuit is removed from the chamber. Finally, the large first metal regions are disconnected from the electrically grounded elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.