Method for testing, burning-in, and manufacturing wafer scale integrated circuits and a packaged wafer assembly produced thereby
US5440241A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1992 |
| Grant date | Aug 8, 1995 |
| Priority date | — |
| Expiry date | Mar 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for probe testing and burning-in integrated circuits formed within dice or chips on a silicon wafer and then optionally either: (1) dicing the wafer into individual chips for shipment or (2) mating the wafer for shipment with a facing substrate having a temperature coefficient of expansion (TCE) matching the TCE of the wafer. Advantageously, the facing substrate is used for both probe and burn-in operations as well as being made a part of the wafer package in option No. 2 above where either the whole silicon wafer or a partial silicon wafer meeting threshold die requirements is to be shipped. In addition, probe and burn-in operations are carried out rapidly at high yields only after all integrated circuit manufacture has been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.