Jerry M. Brooks
170Patents
35h-index
20Co-inventors
86Inventor score
Filing activity: Mar 29, 1991 → Feb 22, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6072233A | Stackable ball grid array package | Electricity | 386 | Expired |
| US5677566A | Semiconductor chip package | Electricity | 376 | Expired |
| US6326244A | Method of making a cavity ball grid array apparatus | Electricity | 316 | Expired |
| US6051878A | Method of constructing stacked packages | Emerging Cross-Sectional Technologies | 243 | Expired |
| US6084297A | Cavity ball grid array apparatus | Electricity | 220 | Expired |
| US6258623A | Low profile multi-IC chip package connector | Emerging Cross-Sectional Technologies | 218 | Expired |
| US6583503B2 | Semiconductor package with stacked substrates and multiple semiconductor dice | Emerging Cross-Sectional Technologies | 218 | Expired |
| US6159764A | Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages | Electricity | 211 | Expired |
| US5994166A | Method of constructing stacked packages | Emerging Cross-Sectional Technologies | 200 | Expired |
| US5973935A | Interdigitated leads-over-chip lead frame for supporting an integrated circuit die | Emerging Cross-Sectional Technologies | 190 | Expired |
| US6225689A | Low profile multi-IC chip package connector | Emerging Cross-Sectional Technologies | 181 | Expired |
| US6072228A | Multi-part lead frame with dissimilar materials and method of manufacturing | Electricity | 173 | Expired |
| US6228548A | Method of making a multichip semiconductor package | Electricity | 171 | Expired |
| US6148509A | Method for supporting an integrated circuit die | Emerging Cross-Sectional Technologies | 158 | Expired |
| US5140405A | Semiconductor assembly utilizing elastomeric single axis conductive interconnect | Electricity | 152 | Expired |
| US6140154A | Multi-part lead frame with dissimilar materials and method of manufacturing | Electricity | 140 | Expired |
| US6344976B1 | Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die | Electricity | 138 | Expired |
| US6313522A | Semiconductor structure having stacked semiconductor devices | Electricity | 137 | Expired |
| US6284571A | Lead frame assemblies with voltage reference plane and IC packages including same | Electricity | 129 | Expired |
| US6429528B1 | Multichip semiconductor package | Electricity | 125 | Expired |
| US6900528B2 | Stacked mass storage flash memory package | Electricity | 118 | Expired |
| US6222265A | Method of constructing stacked packages | Emerging Cross-Sectional Technologies | 117 | Expired |
| US5440241A | Method for testing, burning-in, and manufacturing wafer scale integrated circuits and a packaged wafer assembly produced thereby | Electricity | 90 | Expired |
| US6965160B2 | Semiconductor dice packages employing at least one redistribution layer | Electricity | 77 | Expired |
| US5616953A | Lead frame surface finish enhancement | Electricity | 66 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.