CMOS latchup suppression by localized minority carrier lifetime reduction

US5441900A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Constantin Bulucea · Milpitas, US
• Esin Dermirlioglu · Cupertino, US
• Sheldon Aronowitz · San Jose, US

Key dates

• Filing date: Sep 19, 1994
• Grant date: Aug 15, 1995
• Expiry date: Sep 19, 2014

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/917

Abstract

A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.