Method and system for distributed instruction address translation in a multiscalar data processing system
US5442766A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1992 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Oct 9, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions to the processor units. A memory management unit (MMU) is established which includes a translation buffer and translation algorithms for implementing page table and address block type translations of every effective address within the data processing system into real addresses within memory. A translation array, which includes a small number of translation objects for translating effective addresses into real addresses, is then established within the fetcher unit. The translation objects are periodically and selectively varied, utilizing the translation capability of the memory management unit (MMU), in response to a failure to translate an effective address into a real address within the fetcher unit. A translation object within the translation array is preferably replaced each time the fetcher unit fails to translate an effective address into a real address by replacing the least recen…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.