Method and apparatus for implementing refresh in a synchronous DRAM system
US5446696A · kind A · utility
131Cited by
12References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 2, 1994 |
| Grant date | Aug 29, 1995 |
| Priority date | — |
| Expiry date | Dec 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.