Thermally enhanced semiconductor device having exposed backside and method for making the same
US5450283A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1994 |
| Grant date | Sep 12, 1995 |
| Priority date | — |
| Expiry date | Jan 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thermally enhanced semiconductor device (10) having an exposed backside (22) is described. In one embodiment, a PC board substrate (12) is provided having a pattern of conductive traces (14) on both upper and lower surfaces of the substrate. Electrical continuity is maintained between the two surfaces with conductive vias (16). A semiconductor die (18) is flip-mounted to the upper surface of the substrate. Solder bumps (26) electrically connect the die to the conductive traces, and an underfill (28) couples the active side (20) of the die to the upper surface of the substrate. A package body (40) is formed around the perimeter (24) of the die leaving the inactive backside exposed for enhanced thermal dissipation. The inactive backside can also be coupled to a heat sink for increased thermal dissipation. A plurality of solder balls (42) electrically connected to the conductive traces is attached to the lower surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.