Method for forming a vertically integrated dynamic memory cell
US5451538A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Apr 20, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34). A capacitor (69) is formed overlying and coupled to the vertical transistor (10) in order to form a dynamic random access memory (DRAM) cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.