Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
US5453400A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1993 |
| Grant date | Sep 26, 1995 |
| Priority date | — |
| Expiry date | Jan 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.