Multi-level semiconductor structures having environmentally isolated elements
US5455445A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1994 |
| Grant date | Oct 3, 1995 |
| Priority date | — |
| Expiry date | Jan 21, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/012
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of individual device layers having conductive regions extending therethrough are bonded together before or after one or more circuit elements have been fabricated on each one. Groups of device layers are formed by electrochemically anodizing a wafer of semiconductor material. The wafer is rendered totally porous except for a series of non-porous regions extending therethrough. The wafer is then oxidized and densified to result in a wafer having a plurality of electrically isolated extended contacts. A plurality of wafers are processed in this manner. A variety of integrated circuit devices are then formed on the surface of each wafer. The ability to separately fabricate each wafer obviates trying to incorporate various incompatible processes (required by each device type) on just one wafer surface. Once the processing of all individual wafers is completed, each wafer is bonded to another at appropriate areas, with the extending contact aligned to electrically interconnect each device layer. The wafers are then diced to provide a plurality of multi-level integrated circuit structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.