Programmable dynamic random access memory (DRAM)
US5457659A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1994 |
| Grant date | Oct 10, 1995 |
| Priority date | — |
| Expiry date | Jul 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM which adapted to provide extended data output upon the input of appropriate logic signals is provided. The DRAM includes a CAS before RAS (CBR) detection circuit that controls the data output during a CBR refresh cycle. The operation of the CBR detection circuit is dependent on the state of the output enable (OE) signal during a CBR refresh cycle (e.g., WE-high, CAS-low, RAS-high then low while CAS low). If OE is low, then the CBR detection circuit will trigger a first output mode for the data out buffer (e.g., normal fast page output mode in a non-persistent version and the programmed mode in a persistent version) along with a refresh pulse to the refresh controller. If OE is high then the CBR detection circuit will trigger an extended data output from the data out buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.