Method for fabricating a capacitor cell in the semiconductor memory device having a step portion
US5459094A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 1994 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Feb 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode. By the composite structure of the capacitor storage node including the lower structure having the cylinder shape and the cover type upper structure connected with the lower structure, it is possible to utilize efficiently a three-dimensional space structure and thereby achieve an increase in capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.