Method of making field effect transistor structure of a diving channel device
US5460987A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1994 |
| Grant date | Oct 24, 1995 |
| Priority date | — |
| Expiry date | Dec 27, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
This invention describes a diving channel device structure and a method of forming the diving channel device structure using deep vertical trenches formed in a silicon substrate crossing shallow vertical trenches formed in the same silicon substrate. The deep vertical trenches are filled with a first heavily doped polysilicon to form the sources and drains of field effect transistors. The shallow vertical trenches are filled with a second highly doped polysilicon to form the gates of the transistors. The device structure provides reduced drain and source resistance which remains nearly constant when the device is scaled to smaller dimensions. The device structure also provides reduced leakage currents and a plane topography. The device structure forms a large effective channel width when the device is scaled to smaller dimensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.