Method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up
US5466616A · kind A · utility
21Cited by
20References
7Claims
0Family size
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Key dates
| Filing date | Apr 6, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Apr 6, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/168
Abstract
A method of producing a reduced-size LDMOS transistor having reduced leakage and latch-up possibility by reducing the vertical projective area of the source electrodes of the LDMOS transistor, which is done by forming first trenches to reach a substrate of the LDMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.