Output buffer with boost from voltage supplies
US5469385A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1993 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | May 11, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.