Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch
US5470773A · kind A · utility
24Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1994 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Apr 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/44
Abstract
A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.