Metal interconnect fabrication with dual plasma silicon dioxide deposition and etchback
US5472825A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1993 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Sep 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the fabrication of an integrated circuit, an intermetal dielectric is formed using a plural plasma processes that can be performed without having to transfer the wafer in the interim. This saves on wafer handling. A wafer with a patterned first metal wafer is placed into a plasma chamber. A relatively low-power noble gas plasma is applied to clean the wafer. A reactive plasma treatment is then used to deposit silicon dioxide to a thickness greater than ultimately desired. A noble gas plasma is used to etch back the silicon dioxide. Spin-on glass is then applied. The previous etch back aids the conformance of the spin-on glass to the underlying structure. The spin-on glass can be polished for further planarization. A second silicon dioxide layer can be deposited on top of the spin-on glass. Via apertures can be photolithographically defined through the three-layer dielectric. Finally, second layer metal is deposited and patterned. The method provides for high wafer throughput, while minimizing voids at the interface between the spin-on glass and the underlying silicon dioxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.