Method for fabricating polycide gate MOSFET devices
US5472896A · kind A · utility
38Cited by
15References
4Claims
0Family size
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Key dates
| Filing date | Nov 14, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Nov 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described. After a thin oxide layer is formed by a thermal process, the refractory metal silicide layer is transformed from an amorphous form to a crystalline form that leads to peeling and surface roughness problems in the prior art. This method utilizes an additional ion implantation step to transform the refractory metal silicide layer from the crystalline form back into the amorphous form. Hence, the problems of peeling and surface roughness of the polycide gate can be overcome.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.