Semiconductor integrated circuit device
US5483083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1993 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Mar 9, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.