Electrically erasable programmable read-only memory with an array of one-transistor memory cells
US5483484A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1994 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | May 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate tunneling metal oxide semiconductor transistor is formed on a semiconductive substrate as a cell of electrically erasable programmable read-only memory. The transistor includes a source and a drain spaced apart to define a channel region therebetween in the substrate. An insulated floating gate at least partially overlies the channel region and is capacitively coupled with the substrate. A control gate is insulatively disposed above the conductive layer and spans the channel region. The withstanding voltage of the drain is specifically set to range from a first voltage adapted to be applied to the drain during a read operation to a second voltage applied thereto for forcing the conductive layer to discharge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.