Self-aligned anti-punchthrough implantation process

US5484743A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Joe Ko · Hsinchu, TW
• Chen-Chiu Hsue · Baoshan, TW

Key dates

• Filing date: Feb 27, 1995
• Grant date: Jan 16, 1996
• Expiry date: Feb 27, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601

Abstract

The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.