Selective metal wiring and plug process
US5484747A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 1995 |
| Grant date | Jan 16, 1996 |
| Priority date | — |
| Expiry date | May 25, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/976
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method are provided for forming a plug contact and a metal line pattern in a semiconductor device. A contact hole is etched through a first dielectric layer. A second dielectric layer is formed overlying the first layer having first opening that defines a first metal layer and plug contact. A nucleation layer, such as Ti/TiN or Ti/TiW, is formed on the exposed surfaces of the contact hole and first opening. A planarizing layer is formed which fills the contact hole, and at least partially fills the first openings thereby masking portions of the nucleation layer. Unmasked portions of the nucleation layer are removed and then the planarizing layer is removed. A metal is selectively deposited on the remaining nucleation layer portions to fill the contact hole and substantially filling the first opening. The metal in the first opening forms a plug contact to the bottom surface and a metal line pattern. This process has the advantages of forming two metal levels--i.e., the plug contact and the first metal pattern--with one deposition process as well as defining the metal lines using a selective deposition, not a metal photo/etch process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.