Symbolic routing guidance for wire networks in VLSI circuits
US5485396A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1991 |
| Grant date | Jan 16, 1996 |
| Priority date | — |
| Expiry date | Jun 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floor-plan of component blocks of logical circuits, including the symbolic routing of major connection networks, is produced as part of the process for laying out an integrated circuit on a chip. The floor-plan is produced before performing optimized placement and routing of logical circuits within component blocks of the VLSI circuit. First, the logical circuits are apportioned into component blocks. Then, an initial lay out of the component blocks of the VLSI circuit is performed. The major connection networks are routed between the component blocks so that the major connection networks are connected to connection areas within the component blocks. The initial lay out of component blocks is adjusted as necessary in order to take into account the addition of the major connection networks. Once any needed adjustments are made, routing guidance information is generated as part of the floor plan. The routing guidance information indicates locations and sizes of the major connection networks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.