Method and system for testing an integrated circuit featuring scan design

US5485473A · kind A · utility

Inventors

• Ulich Diebold · Herrenberg, DE
• Peter Rost · Calw, DE
• Manfred Schmidt · Krefeld, DE
• Otto A. Torreiter · Echterdingen, DE
• Rolf Vogt · Oftersheim, DE
• Klaus Wagner-Drebenstedt · Herrenberg, DE

Key dates

• Filing date: Aug 20, 1993
• Grant date: Jan 16, 1996
• Expiry date: Aug 20, 2013

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/307
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The present invention provides for improved testing of an integrated circuit. In order to measure a test signal S from the integrated circuit 1 a multi-pattern is placed in a shift register. The multi-pattern is generated by overlaying at least two test patterns Ax and Bx. Therefore the signal S changes its state in response to only a small amount of shift operations.