Constant delay interconnect for coupling configurable logic blocks
US5490074A · kind A · utility
23Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1995 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Apr 18, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. The interconnect network has longlines and programmable interconnect points (PIP's). PIP's are symmetrical distributed in a partially populated fashion within the interconnect network such that a substantially same signal propagation delay develops for each signal routed along a program-selected longline from a CLB adjacent to that longline to an IOB adjacent to that longline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.