High density ROM with select lines
US5493527A · kind A · utility
5Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1995 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Jan 9, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read only memory cell array and method of operation thereof comprises an array of memory transistor cells, a plurality of word lines, a plurality of bit lines, a plurality of select bit lines, a plurality of bank select lines for enabling reading of a selected bank in the array connected to bank select transistors in the bank, a select even line adapted for enabling reading of even cells in a selected bank connected to select even cell transistors in the bank, and a select odd line adapted for enabling reading of odd cells in a selected bank connected to select odd cell transistors in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.